Without limiting the scope of the invention, this background of the present invention will be described with reference to building a semiconductor wafer-interposer, as an example. After the introduction of the integrated circuit, engineers have worked diligently to produce electronic devices that are smaller and more functional than the previous versions of the devices. Advances in manufacturing techniques allow more components to be integrated into a smaller semiconductor die. More components within the die enable engineers to design devices having greater efficiency and more convenient functions. However, increasing the number of components within the die can adversely affect the size and manufacturing costs of the device.
Each new device design often requires smaller, more efficient semiconductor packages to perform advanced functions and consume less power and space. Die size and number of contact pads influence the size of a semiconductor package. More components within the die require more contact pads, which facilitate electrical connections or interfaces between the die to other systems in the device. However, traditional connection techniques are not very space efficient.
Traditionally, die design was limited because all connections between the components of the die interfacing systems were through the peripheral edges of the chip (for wire bonding) or through a standard pin or pad layout defined by a standardization body, such as the Joint Electrical Dimensional Electronic Committee (JEDEC). The interconnection requirements, therefore, have traditionally driven the die layout.
Although space efficiency may be improved by using a semiconductor wafer-interposer, it is difficult to attached a separate interposer to a semiconductor wafer and maintain close dimensional tolerances. Close tolerance for package height is a requirement for many applications. Typically, thick packages are more reliable and have lower manufacturing costs. In contrast, thin packages may be required for applications where space and weight are at a premium. Additionally, manufacturing a thin package is usually costly because smaller components are more difficult to process and require more precise machinery.
Current manufacturing processes cannot precisely and efficiently control the final height of the package. After the wafer-interposer assembly is diced, the footprint of the resulting semiconductor package is almost the size of the die, which is as small as the package can be without making a smaller die. However, the height of the package cannot be as accurately controlled because it varies according to the method used to construct the wafer-interposer.
Another costly manufacturing process associated with assembling semiconductor packages having interposers is aligning the die with the interposer. The contact pads on the die and the interposer must be aligned and connected to result in a functional semiconductor package. Aligning minute contacts between the die and interposer is an expensive and time intensive process. Current available methods of alignment slow the manufacturing process and increase costs.
Accordingly, there is a need for a system, method and apparatus for building a semiconductor wafer-interposer assembly that overcomes the present manufacturing limitations and inefficiencies.